The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a recess gate of a semiconductor device.
In a typical method for forming a planar gate interconnection line by forming a gate over a flat active region, the current large integration scale of semiconductor devices has caused a channel length to be decreased but an implantation doping concentration to be increased. Accordingly, due to an increased electric field, a junction leakage is generated and thus, it becomes difficult to secure a satisfactory refresh property of a device.
A three-dimensional recess gate process has been suggested to overcome the above described limitations. The three-dimensional recess gate process etches a substrate to form a recess and then, forms a gate over the recess. If the recess gate process is applied, a channel length may be increased and an ion doping concentration may be decreased. As a result, a refresh property of a device may be greatly improved.
FIGS. 1A and 1B illustrate a typical method for fabricating a recess gate of a semiconductor device. As shown in FIG. 1A, an isolation structure 12 is formed in certain portion of a substrate 11 to define an active region 13.
The active region 13 of the substrate 11 is etched to form a plurality of bulb-shaped recesses 14. Each of the bulb-shaped recesses 14 include a first portion formed in vertical pattern 14A and a second portion formed in a bulb pattern 14B. In more details about the formation of the bulb pattern 14B, the vertical pattern 14A is formed and then, a plurality of spacers 15 including oxide-based materials are formed over sidewalls of the vertical pattern 14A. A recess etching process is performed using the spacers 15 as an etch barrier to obtain the bulb pattern 14B.
As shown in FIG. 1B, a pad oxide layer (not shown) and the spacers 15 formed over the sidewalls of the vertical pattern 14A are removed. A gate insulation layer 16 is formed over the substrate 11 including the bulb-shaped recesses 14. A polysilicon layer 17 for a gate conductive layer and a gate metal layer 18 are formed to project over the gate insulation layer 16 while filling the recesses 14. As a result, a plurality of recess gates RG are formed.
Since the spacers 15 formed over the sidewalls of the vertical pattern 14A are used as an etch barrier during the etching of the bulb pattern 14B, a horn identified with a reference letter ‘A’ (see FIG. 1A) may be formed at a portion between the vertical pattern 14A and the bulb pattern 14B during anisotropic etching process.
FIGS. 2A and 2B are transmission electron microscopy (TEM) illustrating a limitation generated during a typical method for fabricating a recess gate. A bulb-shaped recess 24 is formed as shown in FIG. 2A. Although not shown, reference numerals 21, 22, and 23 respectively identify a substrate, an isolation structure, and an active region. As shown in FIG. 2B, a horn identified with a reference letter ‘B’ may be generated at a portion between a vertical pattern 24A and a bulb pattern 24B of the bulb-shaped recess 24 during anisotropic etching process to form the bulb pattern 24B using a spacer insulation layer 25 formed over sidewalls of the bulb pattern 24A as a barrier.
The horn ‘B’ is likely to degrade a property of a subsequent gate insulation layer. The horn ‘B’ becomes a portion at which a stress concentrates, thereby becoming a leakage source. As a result, yields of the device may be decreased.